1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, the improvement of a roll call circuit for detecting an internal test signal.
2. Description of the Related Art
In a semiconductor memory device incorporating normal memory cells and redundancy memory cells, not only a normal decoder for selecting the normal memory cells but also a redundancy decoder for selecting the redundancy memory cells are provided. That is, if a defective memory cell is found in the normal memory calls, an address of such a defective memory address (hereinafter, referred to as a defective address) is written into the redundancy decoder. As a result, when such a defective address is received by the redundancy decoder, the redundany decoder deactivates the normal decoder, and in its place, selects the redundancy memory cell, to thereby replace the defective memory cell with the redundancy memory cell. Thus, the problem of the defective memory cell is alleviated.
The redundancy decoder is usually comprised of a multi-bit fuse-type programmable read-only memory (PROM). Therefore, writing of a defective address into the redundancy decoder is carried out by laser trimming or the like.
In the above-described device, information indicating whether or not the redundancy decoder is surely trimmed must be read from the exterior of the device. In order to satisfy this requirement, in the prior art, an internal test signal generating circuit for generating the above-mentioned information and a roll cell circuit controlled this information are provided. The internal test signal generating circuit is usually comprised of a one-bit fuse-type PROM which is trimmed simultaneously with the trimming of the redundancy decoder. Also, when the internal test signal generating circuit is trimmed, a through current flows through the roll call circuit. Therefore, whether or not the redundancy decoder is trimmed is dependent upon whether or not a through current is detected from the exterior.
A first prior art roll cell circuit includes a load formed by a P-channel MOS transistor and a switching element formed by an N-channel MOS transistor. The load and the switch element are connected in series between a power supply terminal and a ground voltage terminal. The switching element is turned ON and OFF in accordance with the signal of the internal test signal generating circuit. This will be explained later in detail.
In the above-described first prior art roll call circuit, however, when the internal test signal is high, a through current always flows through the roll call circuit, thus increasing the power dissipation.
In order to reduce the power dissipation, in a second prior art roll call circuit, another switching element is added within a current path of the first prior art roll call circuit (see: JP-A-2-146197). Also, in a third prior art roll call circuit, another switching element is added between the internal test signal generating circuit and the first prior art roll call circuit (see: JP-A-3-58398). Only in an initial state after the power is turned ON or the like, is the additional switching element turned ON, thus reducing the power dissipation. This will be explained later in detail.
In the above-described second and third prior art roll call circuits, however, since the load suppresses the through current, the through current cannot be increased, so that it is difficult to determine whether or not the through current flows. Also, although an abnormal through current in an initial state inherently does not have anything to do with the users, the users often complain about this current, since the user is not informed as to the reason for the current.